Abstract: The objective is to design and build a small, high-bandwidth switch.

The Tiny Tera is a small packet switch with an aggregate bandwidth of approximately 1Tera bit per second. The Tiny Tera is a CMOS-based input-queued, variable-size packet switch suitable for a wide range of applications such as a high-performance ATM, IP or Tag switch, the core of an Internet router or as a fast multiprocessor interconnect. Using standard technology, we plan to demonstrate that a very high-bandwidth switch can be built without the need for esoteric optical switching technology. By employing novel scheduling algorithms for both unicast and multicast traffic, the switch will have a maximum throughput close to 100%. Using novel high-speed chip-to-chip serial link technology, we plan to reduce the physical size and complexity of the switch, as well as the system pin-count.

This is joint work with the DSPS R&D Center of Texas Instruments Inc., and is supported by Cisco Systems Inc. and the Stanford University Telecom Center.

 

Tiny-Tera / High Performance Switching
Designed by Wesley Chou, Vicki Shimizu and Rolf Muralt muralt@cs.stanford.edu 
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