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  Subject:   SYSTEM-ON-CHIP TEST STRATEGIES

  Sponsor:   US-JAPAN TECHNOLOGY MANAGEMENT CENTER

  Speaker:   Dr. Yervant Zorain

  Date:   Thursday, April 22, 1999

  Time:   4:15pm - 5:30pm

  Location:   SKILLING AUDITORIUM, Stanford Engineering Quad [look for it in a campus map][new]

  Event URL:   http://fuji.stanford.edu/events

  Sponsor URL:   http://fuji.stanford.edu

  Costs:   *FREE* *OPEN TO THE PUBLIC*

  Contact:   Viji Jagannathan

Talk Abstract: Spurred by technology leading to the availability of millions
of gates per chip, system-level integration is evolving  as a
new paradigm, allowing entire systems to be built on single chips.
This lecture presents the state-of-the-art in system-level
integration and addresses the challenges and current industrial 
practices in the test of embedded cores based system-on-chip.
It discusses the testing requirements for such systems, such as
test access mechanisms for individual cores, system-on-chip
test integration and standardization. The issues of debugging 
embedded cores will also be analyzed and the state-of-art
strategies illustrated. Porting of testability features
of embedded cores will be discussed and different 
plug-and-play test approaches to create system-on-chips 
presented.

Please check website for furter details.

 Event history: Submitted on 09-Apr-1999;


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