by Jorge Cham
Subject:   EE310 SEMINAR - H. Samavati, "12.4mW CMOS Front-End for a 5GHz Wireless-LAN Receiver, "Fractal Capacitors" and
Sponsor:   EE310 Integrated Circuits Technology and Design Seminar
Date:   Tuesday, January 4, 2000
Time:   4:15pm - 5:15pm
Location:   Building 260, Room 007T [look for it in a campus map]
A 12.4mW CMOS Front-End for a 5GHz Wireless-LAN Receiver In this talk I will present a 12.4mW front-end for a 5GHz wireless-LAN receiver fabricated in a 0.24-mm CMOS technology. The chip consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates the image-signal by an additional 12dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascade devices in the LNA core. The LNA/filter combination has a noise figure of 4.8dB and the overall noise figure of the signal path is 5.2dB. The overall IIP3 is -2dBm. -------------------------------------------------------- Fractal Capacitors In this talk, A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottom-plate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fractal structure is implemented with 0.6mm metal spacing and a factor of 2.3 increase in the capacitance per unit area is observed. It is shown that capacitance boost factors in excess of 10 may be possible as technology continues to scale. A CAD tool to automatically generate and analyze custom fractal layouts has been developed.
Event history: Submitted by guerra on 03-Jan-2000;
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